Memory operations & instructions.html (3335B)
1 <?xml version="1.0" encoding="UTF-8"?> 2 <!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> 3 <html><head><link rel="stylesheet" href="sitewide.css" /><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/><meta name="exporter-version" content="Evernote Mac 6.13.1 (455785)"/><meta name="altitude" content="-0.2982466220855713"/><meta name="author" content="Alex Balgavy"/><meta name="created" content="2017-12-11 6:07:47 PM +0000"/><meta name="latitude" content="52.3736534682663"/><meta name="longitude" content="4.836205585752691"/><meta name="source" content="desktop.mac"/><meta name="updated" content="2017-12-11 10:49:57 PM +0000"/><title>Memory operations & instructions</title></head><body><div><span style="font-weight: bold;">Memory operations</span></div><div>to execute an instruction, processor control circuits have to cause word/words containing instruction to be transferred from memory to processor (with operands and results)</div><div>basic operations</div><div><ul><li>read — transfers copy of contents of memory location to processor</li><li>write — transfers item of info from processor to a memory location</li></ul><div><br/></div></div><div><br/></div><div><span style="font-weight: bold;">RISC vs CISC instruction sets</span></div><div>(most processors have a compromise)</div><div><br/></div><div>RISC (Reduced Instruction Set Computers)</div><div><ul><li>simple addressing modes</li><li>each instruction fits in one word</li><li>fewer instructions in set</li><li>arithmetic/logic only on operands in processor registers</li><li>load/store architecture: no direct transfer between memory locations, must be through processor register</li><li>programs tend to be larger in size (more, simpler instructions)</li><ul/></ul></div><div><br/></div><div>CISC (Complex Instruction Set Computers)</div><div><ul><li>more complex addressing modes, e.g.:<br/></li><ul><li>autoincrement— access operand through effective address in passed register, then increment contents of said register</li><li>autodecrement — contents of passed register are decremented and then used as effective address fo operand</li><li>relative — effective address is determined using index mode with PC instead of register</li></ul><li>instructions don’t have to fit into a single word</li><li>more complex instructions</li><li>arithmetic/logic also on both memory locations and registers</li><li>not constrained to load/store architecture</li><ul/></ul></div><div><br/></div><div><span style="font-weight: bold;">Instruction Execution</span></div><div>the processor has a program counter (PC) register, holds address of next instruction</div><div>processor circuits use info in PC to fetch and execute instructions in order of increasing address (straight-line sequencing)</div><div><br/></div><div>executing an instruction</div><div><ol><li>Instruction fetch — instruction fetched from mem location stored in PC and put in instruction register</li><li>Instruction execute — instruction is examined and the operation is performed, PC is incremented by 4.</li></ol><div><br/></div></div><div>branch instructions load new address into PC, allow conditional jumping (jump if greater/less than)</div><div><br/></div><div><br/></div></body></html>